1. Field of the Invention
The present invention relates to a read-only memory system (hereinafter simply called a ROM) such as a mask ROM and a PROM, and more particularly, to a MOS ROM circuit having a read and sense amplifier.
2. Description of the Prior Art
Japanese Laid-Open Patent Publication Nos. 59-75495 and 59-77700, and Japanese Patent Publication No. 59-13117, disclose prior art ROM IC devices.
With the increasing packing density of MOS ROM IC devices, it has been difficult to access the contents of selected memory cells at and near the ends of the word lines at a high rate, because of a larger capacitance associated with the word lines. For example, in a 256-bit EPREOM IC in which polysilicon word lines are used, the access delay due to the word lines occupies one third or more of the entire access time, resulting in a decreased read-out speed.
The problem will be described in detail with reference to FIG. 4. In general, a prior art MOS ROM IC device is used with memory MOS transistors each having their source connected to ground (Vss). Now, for example, in a read operation, when a word line decoder 7 selects a word line 3-1 in response to a row address signal 11 while a data line decoder (not shown) selects a data line 4-n in response to a column address signal 12 (not shown), a memory MOS transistor 2-1n becomes conductive, so that a detection current flows from the drain electrode to source electrode. Since the remaining non-selected MOS transistors form inversion layers under the gate insulating layers thereof, the MOS capacitance between the data line and Vss is determined only by the thickness of the gate insulating layer.
The MOS capacitance is very large and forms an RC ladder delay circuit with the resistance of the word line. In the following read operation, when one of the remaining MOS transistors is selected, the word line decoder has to drive a selected word line acting as a heavy load, so that the read-out speed is greatly decreased due to the delay characteristics of the word line.